本文介紹了為先進封裝設計的3D IC整合部署由系統層級netlist驅動的LVS工作流程時，電子 系統工程師所面臨的兩大挑戰：1)在部署由系統層級 netlist 驅動的流程時，所執行的 netlist 與 netlist 比較檢查；2)連線關係異常，例如領域之間net名稱不同、已知的短路及開路。隨後說明如何針對系統層級LVS使用Siemens Xedition Substrate Integrator (xSI)和Calibre 3DSTACK流 程，來應對這兩個複雜的挑戰。

目前有幾個因素正在整合並推動小晶片設計革命。本白皮書將探討這些因素，並綜整出五個關鍵工作流程，以因應並管理新的相關挑戰。本白皮書將推薦採用工作流程時需要關注的重點領域，以獲得異質整合能力的直接好處，同時建立一套有序的方法採用和遷移流程，最大限度減少中斷並降低風險和成本。這將促使基於異質整合的小晶片設計在主流市場取得一席之地，而不再是僅供大型iDM和無晶圓廠半導體公司獨享。

取得多基板3D IC組裝的預期系統層級連線關係可能是一項挑戰，將多顆晶粒和基板整合到單一封裝中，仍然是半導體產業的主要重點。相較於傳統的電晶體微縮方法，先進封裝有望實現更小的晶片尺寸，節省成本，同時改善效能和功能。

Deca的M-SeriesTM是一種全有機式先晶片平面結構，有望提供一種全新的方法，無需複雜的結構和流程也能實現高密度互連基準的等效密度。Deca Technologies、Siemens EDA與ASE Group攜手合作，對M系列小晶片 測試載具進行了設計、驗證、建構與分析。

In this paper, the authors, as members of the Chiplet Design Exchange (CDX), propose a set of standardized chiplet models that include thermal, physical, mechanical, IO, behavioral, power, signal and power integrity, electrical properties, and test models, as well as documentation to facilitate the integration of the chiplets into a design. Additionally, security traceability assurance is an emerging need to ensure trusted supply chain and operational security of the chiplets and the resulting packaged devices. It is strongly recommended that these models are electronically readable for use in the design work flows

This paper discusses ways in which design teams can apply silicon (IC) type processes to the design and verification of the emerging HDAP packages. High Density Advanced Packaging, or HDAP, is the next-generation architecture for increased functional density, higher performance, lower power, smaller PCB footprints, and thinner profiles. This new “breed” of disruptive packaging technology includes: FOWLP, interposer-based packages (2.5D), CoWoS, high pin-count flip chip, and Wafer-on-Wafer. These new solutions present unique challenges to traditional design tools, are highly disruptive to traditional design methodologies, and disorder the supply chain.